PIC18LF24K Datasheet, PDF (259/594 Pages) –

FIGURE 20-10: EDGE-TRIGGERED HARDWARE LIMIT ONE-SHOT TIMING DIAGRAM
MODE
TMRx_clk
PRx
Instruction⁽¹⁾
ON
TMRx_ers
TMRx
TMRx_postscaled
BS F
0
0b01100
5
BS F
12345
0
1 2 0 12345
Rev. 10-000 201B
5/30/201 4
0
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.