PIC18LF24K Datasheet, PDF (439/594 Pages) –

PIC18(L)F26/45/46K40
31.5 Computation Operation
The ADC module hardware is equipped with post
conversion computation features. These features
provide data post-processing functions that can be
operated on the ADC conversion result, including
digital filtering/averaging and threshold comparison
functions.
FIGURE 31-11: COMPUTATIONAL FEATURES SIMPLIFIED BLOCK DIAGRAM
ADCALC<2:0>
Rev. 10-000260B
8/4/2015
ADRES
ADFILT
Average/
Filter
ADPSIS
1
ADPREV
0
ADSTPT
The operation of the ADC computational features is
controlled by ADMD <2:0> bits in the ADCON2 register.
The module can be operated in one of five modes:
• Basic: This is a legacy mode. In this mode, ADC
conversion occurs on single (ADDSEN = 0) or double
(ADDSEN = 1) samples. ADIF is set after all the
conversion are complete.
• Accumulate: With each trigger, the ADC conversion
result is added to accumulator and ADCNT increments.
ADIF is set after each conversion. ADTIF is set accord-
ing to the calculation mode.
• Average: With each trigger, the ADC conversion
result is added to the accumulator. When the ADRPT
number of samples have been accumulated, a
threshold test is performed. Upon the next trigger, the
accumulator is cleared. For the subsequent tests,
additional ADRPT samples are required to be
accumulated.
• Burst Average: At the trigger, the accumulator is
cleared. The ADC conversion results are then collected
repetitively until ADRPT samples are accumulated and
finally the threshold is tested.
• Low-Pass Filter (LPF): With each trigger, the ADC
conversion result is sent through a filter. When ADRPT
samples have occurred, a threshold test is performed.
Every trigger after that the ADC conversion result is
sent through the filter and another threshold test is
performed.
The five modes are summarized in Table 31-3 below.
ADMD<2:0>
Error
Calculation
ADERR
Threshold
Logic
Set
Interrupt
Flag
ADUTHR ADLTHR
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 439