PIC18LF24K Datasheet, PDF (154/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 13-11: SCANCON0: SCANNER ACCESS CONTROL REGISTER 0
R/W-0/0 R/W/HC-0/0
R-0
R-1
R/W-0/0
U-0
R/W-0/0
R/W-0/0
SCANEN
SCANGO
BUSY
INVALID
INTM
—
MODE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
SCANEN: Scanner Enable bit⁽¹⁾
1 = Scanner is enabled
0 = Scanner is disabled, internal states are reset
SCANGO: Scanner GO bit^{(2, 3)}
1 = When the CRC sends a ready signal, NVM will be accessed according to MDx and data passed to
the client peripheral.
0 = Scanner operations will not occur
BUSY: Scanner Busy Indicator bit⁽⁴⁾
1 = Scanner cycle is in process
0 = Scanner cycle is complete (or never started)
INVALID: Scanner Abort Signal bit
1 = SCANLADRL/H/U has incremented to an invalid address⁽⁶⁾ or the scanner was not setup correctly⁽⁷⁾
0 = SCANLADRL/H/U points to a valid address
INTM: NVM Scanner Interrupt Management Mode Select bit
If MODE = 10:
This bit is ignored
If MODE = 01 (CPU is stalled until all data is transferred):
1 = SCANGO is overridden (to zero) during interrupt operation; scanner resumes after returning from
interrupt
0 = SCANGO is not affected by interrupts, the interrupt response will be affected
If MODE = 00 or 11:
1 = SCANGO is overridden (to zero) during interrupt operation; scan operations resume after returning
from interrupt
0 = Interrupts do not prevent NVM access
Unimplemented: Read as ‘0’
MODE<1:0>: Memory Access Mode bits⁽⁵⁾
11 = Triggered mode
10 = Peek mode
01 = Burst mode
00 = Concurrent mode
Note 1:
2:
3:
4:
5:
6:
7:
Setting SCANEN = 0 (SCANCON0 register) does not affect any other register content.
This bit is cleared when LADR > HADR (and a data cycle is not occurring).
If INTM = 1, this bit is overridden (to zero, but not cleared) during an interrupt response.
BUSY = 1 when the NVM is being accessed, or when the CRC sends a ready signal.
See Table 13-2 for more detailed information.
An invalid address can occur when the entire range of PFM is scanned and the value of LADR rolls over. An
invalid address can also occur if the value in the Scan Low address registers points to a location that is not
mapped in the memory map of the device.
CRCEN and CRCGO bits must be set before setting SCANGO bit. Refer to Section 13.9 “Program Memory
Scan Configuration”.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 154