PIC18LF24K Datasheet, PDF (208/594 Pages) –

PIC18(L)F26/45/46K40
16.0 INTERRUPT-ON-CHANGE
PORTA, PORTB, PORTC and pin RE3 of PORTE can
be configured to operate as Interrupt-on-Change (IOC)
pins on PIC18(L)F2x/4xK40 family devices. An interrupt
can be generated by detecting a signal that has either a
rising edge or a falling edge. Any individual port pin, or
combination of port pins, can be configured to generate
an interrupt. The interrupt-on-change module has the
following features:
• Interrupt-on-Change enable (Master Switch)
• Individual pin configuration
• Rising and falling edge detection
• Individual pin interrupt flags
Figure 16-1 is a block diagram of the IOC module.
16.1 Enabling the Module
To allow individual port pins to generate an interrupt, the
IOCIE bit of the PIE0 register must be set. If the IOCIE
bit is disabled, the edge detection on the pin will still
occur, but an interrupt will not be generated.
16.2 Individual Pin Configuration
For each port pin, a rising edge detector and a falling
edge detector are present. To enable a pin to detect a
rising edge, the associated bit of the IOCxP register is
set. To enable a pin to detect a falling edge, the
associated bit of the IOCxN register is set.
A pin can be configured to detect rising and falling
edges simultaneously by setting both associated bits of
the IOCxP and IOCxN registers, respectively.
16.3 Interrupt Flags
The IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits located
in the IOCAF, IOCBF, IOCCF and IOCEF registers
respectively, are status flags that correspond to the
interrupt-on-change pins of the associated port. If an
expected edge is detected on an appropriately enabled
pin, then the status flag for that pin will be set, and an
interrupt will be generated if the IOCIE bit is set. The
IOCIF bit of the PIR0 register reflects the status of all
IOCAFx, IOCBFx, IOCCFx and IOCEF3 bits.
16.4 Clearing Interrupt Flags
The individual status flags, (IOCAFx, IOCBFx, IOCCFx
and IOCEF3 bits), can be cleared by resetting them to
zero. If another edge is detected during this clearing
operation, the associated status flag will be set at the
end of the sequence, regardless of the value actually
being written.
In order to ensure that no detected edge is lost while
clearing flags, only AND operations masking out known
changed bits should be performed. The following
sequence is an example of what should be performed.
EXAMPLE 16-1:
CLEARING INTERRUPT
FLAGS
(PORTA EXAMPLE)
MOVLW
XORWF
ANDWF
0xff
IOCAF, W
IOCAF, F
16.5 Operation in Sleep
The interrupt-on-change interrupt sequence will wake
the device from Sleep mode, if the IOCIE bit is set.
If an edge is detected while in Sleep mode, the IOCxF
register will be updated prior to the first instruction
executed out of Sleep.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 208