PIC18LF24K Datasheet, PDF (67/594 Pages) –

PIC18(L)F26/45/46K40
7.5 Register Definitions: Peripheral Module Disable
REGISTER 7-1: PMD0: PMD CONTROL REGISTER 0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
SYSCMD
FVRMD
HLVDMD
CRCMD
SCANMD
7
R/W-0/0
NVMMD
R/W-0/0
CLKRMD
R/W-0/0
IOCMD
0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
q = Value depends on condition
bit 7
SYSCMD: Disable Peripheral System Clock Network bit⁽¹⁾
See description in Section 7.4 “System Clock Disable”.
1 = System clock network disabled (FOSC)
0 = System clock network enabled
bit 6
FVRMD: Disable Fixed Voltage Reference bit
1 = FVR module disabled
0 = FVR module enabled
bit 5
HLVDMD: Disable Low-Voltage Detect bit
1 = HLVD module disabled
0 = HLVD module enabled
bit 4
CRCMD: Disable CRC Engine bit
1 = CRC module disabled
0 = CRC module enabled
bit 3
SCANMD: Disable NVM Memory Scanner bit⁽²⁾
1 = NVM Memory Scan module disabled
0 = NVM Memory Scan module enabled
bit 2
NVMMD: NVM Module Disable bit⁽³⁾
1 = All Memory reading and writing is disabled; NVMCON registers cannot be written
0 = NVM module enabled
bit 1
CLKRMD: Disable Clock Reference bit
1 = CLKR module disabled
0 = CLKR module enabled
bit 0
IOCMD: Disable Interrupt-on-Change bit, All Ports
1 = IOC module(s) disabled
0 = IOC module(s) enabled
Note 1:
2:
3:
Clearing the SYSCMD bit disables the system clock (FOSC) to peripherals, however peripherals clocked
by FOSC/4 are not affected.
Subject to SCANE bit in CONFIG4H.
When enabling NVM, a delay of up to 1 µs may be required before accessing data.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 67