PIC18LF24K Datasheet, PDF (194/594 Pages) –

PIC18(L)F26/45/46K40
14.9 INTn Pin Interrupts
PIC18(L)F2x/4xK40 devices have three external inter-
rupt sources which can be assigned to any pin on
PORTA and PORTB using PPS. The external interrupt
sources are edge-triggered. If the corresponding
INTxEDG bit in the INTCON0 register is set (= 1), the
interrupt is triggered by a rising edge. It the bit is clear,
the trigger is on the falling edge.
All external interrupts (INT0, INT1 and INT2) can wake-
up the processor from Idle or Sleep modes if bit INTxE
was set prior to going into those modes. If the Global
Interrupt Enable bit, GIE/GIEH, is set, the processor
will branch to the interrupt vector following wake-up.
Interrupt priority is determined by the value contained
in the interrupt priority bits, INT0IP, INT1IP and INT2IP
of the IPR0 register.
14.10 TMR0 Interrupt
In 8-bit mode (which is the default), an overflow in the
TMR0 register (FFh  00h) will set flag bit, TMR0IF. In
16-bit mode, an overflow in the TMR0H:TMR0L regis-
ter pair (FFFFh 0000h) will set TMR0IF. The interrupt
can be enabled/disabled by setting/clearing enable bit,
TMR0IE of the PIE0 register. Interrupt priority for
Timer0 is determined by the value contained in the
interrupt priority bit, TMR0IP of the IPR0 register. See
Section 18.0 “Timer0 Module” for further details on
the Timer0 module.
14.11 Interrupt-on-Change
An input change on any port pins that support IOC sets
Flag bit, IOCIF of the PIR0 register. The interrupt can
be enabled/disabled by setting/clearing the enable bit,
IOCIE of the PIE0 register. Pins must also be
individually enabled in the IOCxP and IOCxN register.
IOCIF is a read-only bit and the flag can be cleared by
clearing the corresponding IOCxF registers. For more
information refer to Section 16.0 “Interrupt-on-
Change”.
14.12 Context Saving During Interrupts
During interrupts, the return PC address is saved on
the stack. Additionally, the WREG, STATUS and BSR
registers are saved on the fast return stack. If a fast
return from interrupt is not used (see Section
10.2.2 “Fast Register Stack”), the user may need to
save the WREG, STATUS and BSR registers on entry
to the Interrupt Service Routine. Depending on the
user’s application, other registers may also need to be
saved. Example 14-1 saves and restores the WREG,
STATUS and BSR registers during an Interrupt Service
Routine.
EXAMPLE 14-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM
MOVWF
W_TEMP
MOVFF
STATUS, STATUS_TEMP
MOVFF
BSR, BSR_TEMP
;
; USER ISR CODE
;
MOVFF
BSR_TEMP, BSR
MOVF
W_TEMP, W
MOVFF
STATUS_TEMP, STATUS
; W_TEMP is in virtual bank
; STATUS_TEMP located anywhere
; BSR_TEMP located anywhere
; Restore BSR
; Restore WREG
; Restore STATUS
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 194