PIC18LF24K Datasheet, PDF (310/594 Pages) –

PIC18(L)F26/45/46K40
24.14 Register Definitions: CWG Control
Long bit name prefixes for the CWG peripheral is
shown in Table 24-2. Refer to Section 1.4.2.2 “Long
Bit Names” for more information.
TABLE 24-2:
Peripheral
Bit Name Prefix
CWG
CWG
l
REGISTER 24-1: CWG1CON0: CWG CONTROL REGISTER 0
R/W-0/0 R/W/HC-0/0
U-0
U-0
U-0
EN
LD⁽¹⁾
—
—
—
bit 7
R/W-0/0
R/W-0/0
MODE<2:0>
R/W-0/0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
HC = Bit is cleared by hardware
bit 7
bit 6
bit 5-3
bit 2-0
EN: CWG1 Enable bit
1 = Module is enabled
0 = Module is disabled
LD: CWG1 Load Buffers bit⁽¹⁾
1 = Dead-band count buffers to be loaded on CWG data rising edge, following first falling edge after
this bit is set
0 = Buffers remain unchanged
Unimplemented: Read as ‘0’
MODE<2:0>: CWG1 Mode bits
111 = Reserved
110 = Reserved
101 = CWG outputs operate in Push-Pull mode
100 = CWG outputs operate in Half-Bridge mode
011 = CWG outputs operate in Reverse Full-Bridge mode
010 = CWG outputs operate in Forward Full-Bridge mode
001 = CWG outputs operate in Synchronous Steering mode
000 = CWG outputs operate in Asynchronous Steering mode
Note 1: This bit can only be set after EN = 1; it cannot be set in the same cycle when EN is set.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 310