PIC18LF24K Datasheet, PDF (466/594 Pages) –

PIC18(L)F26/45/46K40
32.3 Comparator Control
Each comparator has two control registers: CMxCON0
and CMxCON1.
The CMxCON0 register (see Register 32-1) contains
Control and Status bits for the following:
• Enable
• Output
• Output polarity
• Hysteresis enable
• Timer1 output synchronization
The CMxCON1 register (see Register 32-2) contains
Control bits for the following:
• Interrupt on positive/negative edge enables
• Positive input channel selection
• Negative input channel selection
32.3.1 COMPARATOR ENABLE
Setting the EN bit of the CMxCON0 register enables
the comparator for operation. Clearing the CxEN bit
disables the comparator resulting in minimum current
consumption.
32.3.2 COMPARATOR OUTPUT
The output of the comparator can be monitored by
reading either the CxOUT bit of the CMxCON0 register
or the MCxOUT bit of the CMOUT register.
The comparator output can also be routed to an
external pin through the RxyPPS register (Register 17-2).
The corresponding TRIS bit must be clear to enable the
pin as an output.
Note 1: The internal output of the comparator is
latched with each instruction cycle.
Unless otherwise specified, external out-
puts are not latched.
32.3.3 COMPARATOR OUTPUT POLARITY
Inverting the output of the comparator is functionally
equivalent to swapping the comparator inputs. The
polarity of the comparator output can be inverted by
setting the CxPOL bit of the CMxCON0 register.
Clearing the CxPOL bit results in a non-inverted output.
Table 32-2 shows the output state versus input
conditions, including polarity control.
TABLE 32-2: COMPARATOR OUTPUT
STATE VS. INPUT
CONDITIONS
Input Condition CxPOL
CxOUT
CxVN > CxVP
0
0
CxVN < CxVP
0
1
CxVN > CxVP
1
1
CxVN < CxVP
1
0
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 466