PIC18LF24K Datasheet, PDF (376/594 Pages) –

26.10.7 I²C Master Mode Reception
Master mode reception (Figure 26-29) is enabled by
programming the Receive Enable bit, RCEN bit of the
SSP1CON2 register.
Note:
The MSSP module must be in an Idle
state before the RCEN bit is set or the
RCEN bit will be disregarded.
The Baud Rate Generator begins counting and on each
rollover, the state of the SCL pin changes
(high-to-low/low-to-high) and data is shifted into the
SSPSR. After the falling edge of the eighth clock, the
receive enable flag is automatically cleared, the
contents of the SSPSR are loaded into the SSPxBUF,
the BF flag bit is set, the SSPxIF flag bit is set and the
Baud Rate Generator is suspended from counting,
holding SCL low. The MSSP is now in Idle state
awaiting the next command. When the buffer is read by
the CPU, the BF flag bit is automatically cleared. The
user can then send an Acknowledge bit at the end of
reception by setting the Acknowledge Sequence
Enable, ACKEN bit of the SSPxCON2 register.
26.10.7.1 BF Status Flag
In receive operation, the BF bit is set when an address
or data byte is loaded into SSPxBUF from SSPSR. It is
cleared when the SSPxBUF register is read.
26.10.7.2 SSPOV Status Flag
In receive operation, the SSPOV bit is set when eight
bits are received into the SSPSR and the BF flag bit is
already set from a previous reception.
26.10.7.3 WCOL Status Flag
If the user writes the SSPxBUF when a receive is
already in progress (i.e., SSPSR is still shifting in a data
byte), the WCOL bit is set and the contents of the buffer
are unchanged (the write does not occur).
PIC18(L)F26/45/46K40
26.10.7.4 Typical Receive Sequence:
1. The user generates a Start condition by setting
the SEN bit of the SSPxCON2 register.
2. SSPxIF is set by hardware on completion of the
Start.
3. SSPxIF is cleared by software.
4. User writes SSPxBUF with the slave address to
transmit and the R/W bit set.
5. Address is shifted out the SDA pin until all eight
bits are transmitted. Transmission begins as
soon as SSPxBUF is written to.
6. The MSSP module shifts in the ACK bit from the
slave device and writes its value into the
ACKSTAT bit of the SSPxCON2 register.
7. The MSSP module generates an interrupt at the
end of the ninth clock cycle by setting the
SSPxIF bit.
8. User sets the RCEN bit of the SSPxCON2 regis-
ter and the master clocks in a byte from the slave.
9. After the eighth falling edge of SCL, SSPxIF and
BF are set.
10. Master clears SSPxIF and reads the received
byte from SSPUF, clears BF.
11. Master sets the ACK value sent to slave in the
ACKDT bit of the SSPxCON2 register and initi-
ates the ACK by setting the ACKEN bit.
12. Master’s ACK is clocked out to the slave and
SSPxIF is set.
13. User clears SSPxIF.
14. Steps 8-13 are repeated for each received byte
from the slave.
15. Master sends a not ACK or Stop to end
communication.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 376