PIC18LF24K Datasheet, PDF (335/594 Pages) –

PIC18(L)F26/45/46K40
REGISTER 26-4: SSPxBUF: MSSP DATA BUFFER REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
BUF<7:0>
bit 7
R/W-x
R/W-x
R/W-x
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
bit 7-0
BUF<7:0>: MSSP Buffer bits
REGISTER 26-5: SSPxADD: MSSP ADDRESS REGISTER (SPI MODE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADD<7:0>
bit 7
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
Master mode: SPI mode
bit 7-0
Baud Rate Clock Divider bits
SCK/SCL pin clock period = ((SSPxADD<7:0> + 1) *4)/FOSC
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 335