PIC18LF24K Datasheet, PDF (303/594 Pages) –

PIC18(L)F26/45/46K40
24.7 Rising Edge and Reverse Dead
Band
In Half-Bridge mode, the rising edge dead band delays
the turn-on of the CWG1A output after the rising edge
of the CWG data input. In Full-Bridge mode, the
reverse dead-band delay is only inserted when
changing directions from Forward mode to Reverse
mode, and only the modulated output CWG1B is
affected.
The CWG1DBR register determines the duration of the
dead-band interval on the rising edge of the input
source signal. This duration is from 0 to 64 periods of
the CWG clock.
Dead band is always initiated on the edge of the input
source signal. A count of zero indicates that no dead
band is present.
If the input source signal reverses polarity before the
dead-band count is completed, then no signal will be
seen on the respective output.
The CWG1DBR register value is double-buffered.
When EN = 0 (Register 24-1), the buffer is loaded
when CWG1DBR is written. If EN = 1, then the buffer
will be loaded at the rising edge following the first falling
edge of the data input, after the LD bit (Register 24-1)
is set. Refer to Figure 24-12 for an example.
24.8 Falling Edge and Forward Dead
Band
In Half-Bridge mode, the falling edge dead band delays
the turn-on of the CWG1B output at the falling edge of
the CWG data input. In Full-Bridge mode, the forward
dead-band delay is only inserted when changing direc-
tions from Reverse mode to Forward mode, and only
the modulated output CWG1D is affected.
The CWG1DBF register determines the duration of the
dead-band interval on the falling edge of the input
source signal. This duration is from zero to 64 periods
of CWG clock.
Dead-band delay is always initiated on the edge of the
input source signal. A count of zero indicates that no
dead band is present.
If the input source signal reverses polarity before the
dead-band count is completed, then no signal will be
seen on the respective output.
The CWG1DBF register value is double-buffered.
When EN = 0 (Register 24-1), the buffer is loaded
when CWG1DBF is written. If EN = 1, then the buffer
will be loaded at the rising edge following the first
falling edge of the data input after the LD (Register 24-
1) is set. Refer to Figure 24-13 for an example.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 303