PIC18LF24K Datasheet, PDF (163/594 Pages) –

PIC18(L)F26/45/46K40
TABLE 13-2: SUMMARY OF SCANNER MODES
MODE<1:0>
First Scan Access
Description
CPU Operation
11 Triggered
10 Peek
As soon as possible
following a trigger
At the first dead cycle
01 Burst
As soon as possible
00 Concurrent
Stalled during NVM access
Timing is unaffected
Stalled during NVM access
CPU resumes execution following
each access
CPU continues execution following
each access
CPU suspended until scan
completes
CPU resumes execution following
each access
13.11.5 INTERRUPT INTERACTION
The INTM bit of the SCANCON0 register controls the
scanner’s response to interrupts depending on which
mode the NVM scanner is in, as described in Table 13-3.
TABLE 13-3: SCAN INTERRUPT MODES
MODE<1:0>
INTM
MODE == Burst
MODE == CONCURENT or
TRIGGERED
MODE ==PEEK
Interrupt overrides SCANGO (to Scanner suspended during
zero) to pause the burst and the interrupt response (SCANGO = 0);
1 interrupt handler executes at full interrupt executes at full speed This bit is ignored
speed; Scanner Burst resumes and scan resumes when the
when interrupt completes.
interrupt is complete.
Interrupts do not override
SCANGO, and the scan (burst)
operation will continue; interrupt Scanner accesses NVM during
0 _{response will be delayed until scan interrupt response.}
completes (latency will be
increased).
This bit is ignored
In general, if INTM = 0, the scanner will take
precedence over the interrupt, resulting in decreased
interrupt processing speed and/or increased interrupt
response latency. If INTM = 1, the interrupt will take
precedence and have a better speed, delaying the
memory scan.
13.11.6 WWDT INTERACTION
Operation of the WWDT is not affected by scanner
activity. Hence, it is possible that long scans,
particularly in Burst mode, may exceed the WWDT
time-out period and result in an undesired device
Reset. This should be considered when performing
memory scans with an application that also utilizes
WWDT.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 163