PIC18LF24K Datasheet, PDF (250/594 Pages) –

PIC18(L)F26/45/46K40
20.2 Timer2 Operation
The 3-bit prescaler on the clock input allows for several
prescaler options, from direct input to divide-by-128.
These options are selected by the prescaler control bits
CKPS<2:0> of the T2CON register.
The value of TMR2 is compared to that of the Period
register, PR2, on each clock cycle. When the two values
match, the comparator resets the value of TMR2 to 00h
on the next cycle and drives the 4-bit output
counter/postscaler (see Section 20.3 “Timer2
Interrupt”). In addition, the Timer can be Reset through
the use of an external Reset signal as outlined in
Section 20.5 “External Reset Sources”.
The TMR2 and PR2 registers are both directly readable
and writable. The TMR2 register is cleared on any
device Reset, whereas the PR2 register initializes to
FFh. Both the prescaler and postscaler counters are
cleared on the following events:
• a write to the TMR2 register
• a write to the T2CON register
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• MCLR Reset
• Windowed Watchdog Timer (WWDT) Reset
• Stack Overflow Reset
• Stack Underflow Reset
• RESET Instruction
• External Reset Source events, which resets the
timer.
Note: TMR2 is not cleared when T2CON is
written.
20.3 Timer2 Interrupt
Timer2 can also generate a device interrupt. The
interrupt is generated when the postscaler counter
matches one of 16 postscale options (from 1:1 through
1:16), which is selected with the postscaler control bits,
OUTPS<3:0> of the T2CON register. The interrupt is
enabled by setting the TMR2 Interrupt Enable bit,
TMR2IE, of the PIE4 register. The interrupt timing is
illustrated in Figure 20-3.
FIGURE 20-3:
TIMER2 PRESCALER, POSTSCALER, AND INTERRUPT TIMING DIAGRAM
CKPS
0b010
Rev. 10-000205A
4/7/2016
PRx
1
OUTPS
0b0001
TMRx_clk
TMRx
0
1
0
1
0
1
0
TMRx_postscaled
TMRxIF
(1)
(2)
(1)
Note 1: Setting the interrupt flag is synchronized with the instruction clock.
Synchronization may take as many as 2 instruction cycles
2: Cleared by software.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 250