PIC18LF24K Datasheet, PDF (31/594 Pages) –

PIC18(L)F26/45/46K40
3.3
Code Protection
Code protection allows the device to be protected from
unauthorized access. Program memory protection and
data memory are controlled independently. Internal
access to the program memory is unaffected by any
code protection setting.
3.3.1 PROGRAM MEMORY PROTECTION
The entire program memory space is protected from
external reads and writes by the CP bit in Configuration
Words. When CP = 0, external reads and writes of
program memory are inhibited and a read will return all
‘0’s. The CPU can continue to read program memory,
regardless of the protection bit settings. Self-writing the
program memory is dependent upon the write
protection setting. See Section 3.4 “Write
Protection” for more information.
3.3.2 DATA MEMORY PROTECTION
The entire Data EEPROM Memory space is protected
from external reads and writes by the CPD bit in the
Configuration Words. When CPD = 0, external reads
and writes of Data EEPROM Memory are inhibited and
a read will return all ‘0’s. The CPU can continue to read
Data EEPROM Memory regardless of the protection bit
settings.
3.4 Write Protection
Write protection allows the device to be protected from
unintended self-writes. Applications, such as boot
loader software, can be protected while allowing other
regions of the program memory to be modified.
The WRT<1:0> bits in Configuration Words define the
size of the program memory block that is protected.
3.5 User ID
Eight words in the memory space (200000h-200000Fh)
are designated as ID locations where the user can
store checksum or other code identification numbers.
These locations are readable and writable during
normal execution. See Section 11.2 “User ID, Device
ID and Configuration Word Access” for more
information on accessing these memory locations. For
more information on checksum calculation, see the
“PIC18(L)F2X/4XK40
Memory
Programming
Specification” (DS40001772).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 31