PIC18LF24K Datasheet, PDF (429/594 Pages) –

PIC18(L)F26/45/46K40
31.1.5 INTERRUPTS
The ADC module allows for the ability to generate an
interrupt upon completion of an Analog-to-Digital
conversion. The ADC Interrupt Flag is the ADIF bit in
the PIR1 register. The ADC Interrupt Enable is the
ADIE bit in the PIE1 register. The ADIF bit must be
cleared in software.
Note 1: The ADIF bit is set at the completion of
every conversion, regardless of whether
or not the ADC interrupt is enabled.
2: The ADC operates during Sleep only
when the FRC oscillator is selected.
This interrupt can be generated while the device is
operating or while in Sleep. If the device is in Sleep, the
interrupt will wake-up the device. Upon waking from
Sleep, the next instruction following the SLEEP
instruction is always executed. If the user is attempting
to wake-up from Sleep and resume in-line code
execution, the ADIE bit of the PIE1 register and the
PEIE bit of the INTCON register must both be set and
the GIE bit of the INTCON register must be cleared. If
all three of these bits are set, the execution will switch
to the Interrupt Service Routine.
31.1.6 RESULT FORMATTING
The 10-bit ADC conversion result can be supplied in
two formats, left justified or right justified. The ADFM
bits of the ADCON0 register controls the output format.
Figure 31-3 shows the two output formats.
Writes to the ADRES register pair are always right
justified regardless of the selected format mode. There-
fore, data read after writing to ADRES when
ADFRM0 = 0 will be shifted left six places. For exam-
ple, writing 0xFF to ADRESL will be read as 0xC0 in
ADRESL and 0x3F logical OR’d with whatever was in
the two MS bits in ADRESH.
FIGURE 31-3:
10-BIT ADC CONVERSION RESULT FORMAT
ADRESH
(ADFM = 0) MSB
bit 7
bit 0
10-bit ADC Result
(ADFM = 1)
bit 7
MSB
bit 0
Unimplemented: Read as ‘0’
ADRESL
LSB
bit 7
bit 0
Unimplemented: Read as ‘0’
LSB
bit 7
bit 0
10-bit ADC Result
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 429