PIC18LF24K Datasheet, PDF (80/594 Pages) –

PIC18(L)F26/45/46K40
8.13 Determining the Cause of a Reset
Upon any Reset, multiple bits in the STATUS and
PCON0 registers are updated to indicate the cause of
the Reset. Table 8-3 shows the Reset conditions of
these registers.
TABLE 8-3: RESET CONDITION FOR SPECIAL REGISTERS
Condition
Program
Counter
STATUS
Register^(2,3)
PCON0
Register
Power-on Reset
Brown-out Reset
0
-110 0000
0011 110x
0
-110 0000
0011 11u0
MCLR Reset during normal operation
0
-uuu uuuu
uuuu 0uuu
MCLR Reset during Sleep
WDT Time-out Reset
WDT Wake-up from Sleep
WWDT Window Violation Reset
Interrupt Wake-up from Sleep
0
0
PC + 2
0
PC + 2⁽¹⁾
-10u uuuu
-0uu uuuu
-00u uuuu
-uuu uuuu
-10u 0uuu
uuuu 0uuu
uuu0 uuuu
uuuu uuuu
uu0u uuuu
uuuu uuuu
RESET Instruction Executed
0
-uuu uuuu
uuuu u0uu
Stack Overflow Reset (STVREN = 1)
0
-uuu uuuu
1uuu uuuu
Stack Underflow Reset (STVREN = 1)
0
-uuu uuuu
u1uu uuuu
Legend: u = unchanged, x = unknown, — = unimplemented bit, reads as ‘0’.
Note 1: When the wake-up is due to an interrupt and Global Interrupt Enable bit (GIE) is set the return address is
pushed on the stack and PC is loaded with the corresponding interrupt vector (depending on source, high
or low priority) after execution of PC + 2.
2: If a Status bit is not implemented, that bit will be read as ^‘0^’.
3: Status bits Z, C, DC are reset by POR/BOR (Register 10-2).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 80