PIC18LF24K Datasheet, PDF (89/594 Pages) –

PIC18(L)F26/45/46K40
9.7 Operation During Sleep
When the device enters Sleep, the WWDT is cleared.
If the WWDT is enabled during Sleep, the WWDT
resumes counting. When the device exits Sleep, the
WWDT is cleared again.
The WWDT remains clear until the Oscillator Start-up
Timer (OST) completes, if enabled. See Section
4.3.1.3 “Oscillator Start-up Timer (OST)” for more
information on the OST.
When a WWDT time-out occurs while the device is in
Sleep, no Reset is generated. Instead, the device
wakes up and resumes operation. The TO and PD bits
in the STATUS register are changed to indicate the
event. The RWDT bit in the PCON0 register can also be
used. See Section 10.0 “Memory Organization” for
more information.
TABLE 9-2: WWDT CLEARING CONDITIONS
Conditions
WDTE<1:0> = 00
WDTE<1:0> = 01 and SEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Oscillator Fail Detected
Exit Sleep + System Clock = SOSC, EXTRC, INTOSC, EXTCLK
Exit Sleep + System Clock = XT, HS, LP
Change INTOSC divider (IRCF bits)
FIGURE 9-2:
WINDOW PERIOD AND DELAY
CLRWDT Instruction
(or other WDT reset)
Window Period
WWDT
Cleared
Cleared until the end of OST
Unaffected
Rev. 10-000 163A
11/8/201 3
Window Closed
Window Delay
(window violation can occur)
Window Open
Time-out Event
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 89