PIC18LF24K Datasheet, PDF (44/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 4-3:
QUARTZ CRYSTAL
OPERATION (LP, XT OR
HS MODE)
PIC^® MCU
C1
Quartz
Crystal
OSC1/CLKIN
RF⁽²⁾
To Internal
Logic
Sleep
C2
RS⁽¹⁾
OSC2/CLKOUT
Note 1:
2:
A series resistor (RS) may be required for
quartz crystals with low drive level.
The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
FIGURE 4-4:
CERAMIC RESONATOR
OPERATION
(XT OR HS MODE)
PIC^® MCU
OSC1/CLKIN
C1
To Internal
Logic
RP⁽³⁾
RF⁽²⁾
Sleep
C2 _{Ceramic RS}⁽¹⁾
Resonator
OSC2/CLKOUT
Note 1: A series resistor (RS) may be required for
ceramic resonators with low drive level.
2: The value of RF varies with the Oscillator mode
selected (typically between 2 M to 10 M.
3: An additional parallel feedback resistor (RP)
may be required for proper ceramic resonator
operation.
4.3.1.3 Oscillator Start-up Timer (OST)
If the oscillator module is configured for LP, XT or HS
modes, the Oscillator Start-up Timer (OST) counts
1024 oscillations from OSC1. This occurs following a
Power-on Reset (POR), or a wake-up from Sleep. The
OST ensures that the oscillator circuit, using a quartz
crystal resonator or ceramic resonator, has started and
is providing a stable system clock to the oscillator
module.
4.3.1.4 4x PLL
The oscillator module contains a 4x PLL that can be
used with the external clock sources to provide a
system clock source. The input frequency for the PLL
must fall within specifications. See the PLL Clock
Timing Specifications in Table 37-9.
The PLL can be enabled for use by one of two
methods:
1. Program the RSTOSC bits in the Configuration
Word 1 to 010 (enable EXTOSC with 4x PLL).
2. Write the NOSC bits in the OSCCON1 register
to 010 (enable EXTOSC with 4x PLL).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 44