PIC18LF24K Datasheet, PDF (196/594 Pages) –

PIC18(L)F26/45/46K40
15.0 I/O PORTS
TABLE 15-1: PORT AVAILABILITY PER
DEVICE
Device
PIC18(L)F26K40
PIC18(L)F45/46K40
●●●
●
●●●●●
Each port has eight registers to control the operation.
These registers are:
• PORTx registers (reads the levels on the pins of
the device)
• LATx registers (output latch)
• TRISx registers (data direction)
• ANSELx registers (analog select)
• WPUx registers (weak pull-up)
• INLVLx (input level control)
• SLRCONx registers (slew rate control)
• ODCONx registers (open-drain control)
Most port pins share functions with device peripherals,
both analog and digital. In general, when a peripheral
is enabled on a port pin, that pin cannot be used as a
general purpose output; however, the pin can still be
read.
The Data Latch (LATx registers) is useful for
read-modify-write operations on the value that the I/O
pins are driving.
A write operation to the LATx register has the same
effect as a write to the corresponding PORTx register.
A read of the LATx register reads of the values held in
the I/O PORT latches, while a read of the PORTx
register reads the actual I/O pin value.
Ports that support analog inputs have an associated
ANSELx register. When an ANSELx bit is set, the
digital input buffer associated with that bit is disabled.
Disabling the input buffer prevents analog signal levels
on the pin between a logic high and low from causing
excessive current in the logic input circuitry. A
simplified model of a generic I/O port, without the
interfaces to other peripherals, is shown in Figure 15-1.
FIGURE 15-1:
GENERIC I/O PORT
OPERATION
Write LATx
Write PORTx
Data Bus
Read LATx
D
Q
CK
Data Register
TRISx
Read PORTx
To digital peripherals
To analog peripherals
ANSELx
VDD
I/O pin
VSS
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 196