PIC18LF24K Datasheet, PDF (36/594 Pages) –

PIC18(L)F26/45/46K40
4.2 Register Definitions: Oscillator Control
REGISTER 4-1: OSCCON1: OSCILLATOR CONTROL REGISTER1
U-0
R/W-f/f
R/W-f/f
R/W-f/f
R/W-q/q
R/W-q/q
R/W-q/q
—
NOSC<2:0>
NDIV<3:0>
bit 7
R/W-q/q
bit 0
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
f = determined by fuse setting
q = Reset value is determined by hardware
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘0’
NOSC<2:0>: New Oscillator Source Request bits^(1,2,3)
The setting requests a source oscillator and PLL combination per Table 4-2.
POR value = RSTOSC (Register 3-1).
NDIV<3:0>: New Divider Selection Request bits^(2,3)
The setting determines the new postscaler division ratio per Table 4-2.
Note 1: The default value (f/f) is determined by the RSTOSC Configuration bits. See Table 4-1below.
2: If NOSC is written with a reserved value (Table 4-2), the operation is ignored and neither NOSC nor NDIV is
written.
3: When CSWEN = 0, this register is read-only and cannot be changed from the POR value.
TABLE 4-1: DEFAULT OSCILLATOR SETTINGS
RSTOSC
SFR Reset Values
NOSC/COSC
CDIV
OSCFRQ
Initial FOSC Frequency
111
111
1:1
EXTOSC per FEXTOSC
110
110
4:1
FOSC = 1 MHz (4 MHz/4)
4 MHz
101
101
1:1
LFINTOSC
100
100
1:1
SOSC
011
Reserved
010
010
1:1
4 MHz
EXTOSC + 4xPLL (1)
001
Reserved
000
110
1:1
64 MHz
FOSC = 64 MHZ
Note 1: EXTOSC must meet the PLL specifications (Table 37-9).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 36