PIC18LF24K Datasheet, PDF (198/594 Pages) –

PIC18(L)F26/45/46K40
15.2.5 SLEW RATE CONTROL
The SLRCONx register (Register 15-7) controls the
slew rate option for each port pin. Slew rate for each
port pin can be controlled independently. When an
SLRCONx bit is set, the corresponding port pin drive is
slew rate limited. When an SLRCONx bit is cleared,
The corresponding port pin drive slews at the maximum
rate possible.
15.2.6 INPUT THRESHOLD CONTROL
The INLVLx register (Register 15-8) controls the input
voltage threshold for each of the available PORTx input
pins. A selection between the Schmitt Trigger CMOS or
the TTL compatible thresholds is available. The input
threshold is important in determining the value of a read
of the PORTx register and also the level at which an
interrupt-on-change occurs, if that feature is enabled.
See Table 37-8 for more information on threshold
levels.
Note:
Changing the input threshold selection
should be performed while all peripheral
modules are disabled. Changing the
threshold level during the time a module is
active may inadvertently generate a
transition associated with an input pin,
regardless of the actual voltage level on
that pin.
15.2.7 WEAK PULL-UP CONTROL
The WPUx register (Register 15-5) controls the
individual weak pull-ups for each port pin.
15.2.8
EDGE SELECTABLE
INTERRUPT-ON-CHANGE
An interrupt can be generated by detecting a signal at
the port pin that has either a rising edge or a falling
edge. Any individual pin can be configured to generate
an interrupt. The interrupt-on-change module is pres-
ent on all the pins that are common between 28-pin and
40/44-pin devices. For further details about the IOC
module refer to Section 16.0 “Interrupt-on-Change”.
15.3 PORTE Registers
Depending on the device selected, PORTE is
implemented in two different ways.
15.3.1 PORTE ON 40/44-PIN DEVICES
For PIC18(L)F4xK40 devices, PORTE is a 4-bit wide
port. Three pins (RE0, RE1 and RE2) are individually
configurable as inputs or outputs. These pins have
Schmitt Trigger input buffers. When selected as an
analog input, these pins will read as ‘0’s.
The corresponding data direction register is TRISE.
Setting a TRISE bit (= 1) will make the corresponding
PORTE pin an input (i.e., disable the output driver).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., enable the output driver and
put the contents of the output latch on the selected pin).
TRISE controls the direction of the REx pins, even
when they are being used as analog pins. The user
must make sure to keep the pins configured as inputs
when using them as analog inputs. RE<2:0> bits have
other registers associated with them (i.e., ANSELE,
WPUE, INLVLE, SLRCONE and ODCONE). The
functionality is similar to the other ports.
The Data Latch register (LATE) is also memory
mapped. Read-modify-write operations on the LATE
register read and write the latched output value for
PORTE.
Note: On a Power-on Reset, RE<2:0> are
configured as analog inputs.
The fourth pin of PORTE (MCLR/VPP/RE3) is an input-
only pin. Its operation is controlled by the MCLRE
Configuration bit. When selected as a port pin
(MCLRE = 0), it functions as a digital input-only pin; as
such, it does not have TRIS or LAT bits associated with its
operation. Otherwise, it functions as the device’s Master
Clear input. In either configuration, RE3 also functions as
the programming voltage input during programming.
RE3 in PORTE register is a read-only bit and will read ‘1’
when MCLRE = 1 (i.e., Master Clear enabled).
Note:
On a Power-on Reset, RE3 is enabled as
a digital input only if Master Clear
functionality is disabled.
EXAMPLE 15-2: INITIALIZING PORTE
CLRF
CLRF
CLRF
MOVLW
MOVWF
PORTE
LATE
ANSELE
05h
TRISE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Configure analog pins
; for digital only
; Value used to
; initialize data
; direction
; Set RE<0> as input
; RE<1> as output
; RE<2> as input
15.3.2 PORTE ON 28-PIN DEVICES
For PIC18(L)F2xK40 devices, PORTE is only available
when Master Clear functionality is disabled
(MCLRE = 0). In this case, PORTE is a single bit, input-
only port comprised of RE3 only. The pin operates as
previously described. RE3 in PORTE register is a read-
only bit and will read ‘1’ when MCLRE = 1 (i.e., Master
Clear enabled).
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 198