PIC18LF24K Datasheet, PDF (254/594 Pages) –

PIC18(L)F26/45/46K40
20.6.3
EDGE-TRIGGERED HARDWARE
LIMIT MODE
In Edge-Triggered Hardware Limit mode the timer can
be reset by the TMRx_ers external signal before the
timer reaches the period count. Three types of Resets
are possible:
• Reset on rising or falling edge
(MODE<4:0> = 00011)
• Reset on rising edge (MODE<4:0> = 00100)
• Reset on falling edge (MODE<4:0> = 00101)
When the timer is used in conjunction with the CCP in
PWM mode then an early Reset shortens the period
and restarts the PWM pulse after a two clock delay.
Refer to Figure 20-6.
FIGURE 20-6:
EDGE-TRIGGERED HARDWARE LIMIT MODE TIMING DIAGRAM
MODE
0b00100
Rev. 10-000 197B
5/30/201 4
TMRx_clk
PRx
Instruction⁽¹⁾
BS F
5
BCF BSF
ON
TMRx_ers
TMRx 0 1 2
0 123450 1 234501
TMRx_postscaled
PWM Duty
Cycle
3
PWM Output
Note 1: BSF and BCF represent Bit-Set File and Bit-Clear File instructions executed by the CPU to
set or clear the ON bit of TxCON. CPU execution is asynchronous to the timer clock input.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 254