PIC18LF24K Datasheet, PDF (427/594 Pages) –

PIC18(L)F26/45/46K40
31.1 ADC Configuration
When configuring and using the ADC the following
functions must be considered:
• Port configuration
• Channel selection
• ADC voltage reference selection
• ADC conversion clock source
• Interrupt control
• Result formatting
• Conversion Trigger Selection
• ADC Acquisition Time
• ADC Precharge Time
• Additional Sample and Hold Capacitor
• Single/Double Sample Conversion
• Guard Ring Outputs
31.1.1 PORT CONFIGURATION
The ADC can be used to convert both analog and
digital signals. When converting analog signals, the I/O
pin should be configured for analog by setting the
associated TRIS and ANSEL bits. Refer to Section
15.0 “I/O Ports” for more information.
Note:
Analog voltages on any pin that is defined
as a digital input may cause the input
buffer to conduct excess current.
31.1.2 CHANNEL SELECTION
There are several channel selections available:
• Eight PORTA pins (RA<7:0>)
• Eight PORTB pins (RB<7:0>)
• Eight PORTC pins (RC<7:0>)
• Eight PORTD pins (RD<7:0>), PIC18(L)F45/46K40
only)
• Three PORTE pins (RE<2:0>), PIC18(L)F45/46K40
only)
• Temperature Indicator
• DAC output
• Fixed Voltage Reference (FVR)
• AVSS (ground)
The ADPCH register determines which channel is
connected to the sample and hold circuit.
When changing channels, a delay is required before
starting the next conversion. 0
Refer to Section 31.2 “ADC Operation” for more informa-
tion.
31.1.3 ADC VOLTAGE REFERENCE
The ADPREF<1:0> bits of the ADREF register provide
control of the positive voltage reference. The positive
voltage reference can be:
• VREF+ pin
• VDD
• FVR 1.024V
• FVR 2.048V
• FVR 4.096V
The ADNREF bit of the ADREF register provides
control of the negative voltage reference. The negative
voltage reference can be:
• VREF- pin
• VSS
See Section 28.0 “Fixed Voltage Reference (FVR)”
for more details on the Fixed Voltage Reference.
31.1.4 CONVERSION CLOCK
The source of the conversion clock is software
selectable via the ADCLK register and the ADCS bits of
the ADCON0 register. There are 66 possible clock
options:
• FOSC/2
• FOSC/4
• FOSC/6
• FOSC/8
• FOSC/10
.
.
.
• FOSC/128
• FRC (dedicated RC oscillator)
The time to complete one bit conversion is defined as
TAD. One full 10-bit conversion requires 11.5 TAD
periods as shown in Figure 31-2.
For correct conversion, the appropriate TAD specification
must be met. Refer to Table 37-14 for more information.
Table 31-1 gives examples of appropriate ADC clock
selections.
Note 1: Unless using the FRC, any changes in the
system clock frequency will change the
ADC clock frequency, which may
adversely affect the ADC result.
2: The internal control logic of the ADC runs
off of the clock selected by the ADCS bit
of ADCON0. What this can mean is when
the ADCS bit of ADCON0 is set to ‘1’
(ADC runs on FRC), there may be
unexpected delays in operation when
setting ADC control bits.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 427