PIC18LF24K Datasheet, PDF (134/594 Pages) –

PIC18(L)F26/45/46K40
FIGURE 11-8:
TABLE WRITES TO PROGRAM FLASH MEMORY
TABLAT
Write Register
8
8
8
TBLPTR = xxxx00
TBLPTR = xxxx01
TBLPTR = xxxx02
Holding Register
Holding Register
Holding Register
8
TBLPTR = xxxxYY⁽¹⁾
Holding Register
Program Memory
Note 1: Refer to Table 11-3 for number of holding registers (e.g., YY = 3F for 64 holding registers).
11.1.6.1
Program Flash Memory Write
Sequence
The sequence of events for programming an internal
program memory location should be:
1. Read appropriate number of bytes into RAM.
Refer to Table 11-2 for Write latch size.
2. Update data values in RAM as necessary.
3. Load Table Pointer register with address being
erased.
4. Execute the block erase procedure.
5. Load Table Pointer register with address of first
byte being written.
6. Write the n-byte block into the holding registers
with auto-increment. Refer to Table 11-2 for
Write latch size.
7. Set NVMREG<1:0> bits to point to program
memory.
8. Clear FREE bit and set WREN bit in NVMCON1
register.
9. Disable interrupts.
10. Execute the unlock sequence (see Section
11.1.4 “NVM Unlock Sequence”).
11. WR bit is set in NVMCON1 register.
12. The CPU will stall for the duration of the write
(about 2 ms using internal timer).
13. Re-enable interrupts.
14. Verify the memory (table read).
This procedure will require about 6 ms to update each
write block of memory. An example of the required code
is given in Example 11-4.
Note:
Before setting the WR bit, the Table
Pointer address needs to be within the
intended address range of the bytes in the
holding registers.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 134