PIC18LF24K Datasheet, PDF (270/594 Pages) –

PIC18(L)F26/45/46K40
21.3.3 SOFTWARE INTERRUPT MODE
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE Interrupt Priority bit of the PIE6 register clear
to avoid false interrupts. Additionally, the user should
clear the CCPxIF interrupt flag bit of the PIR6 register
following any change in Operating mode.
Note:
Clocking Timer1 from the system clock
(FOSC) should not be used in Capture
mode. In order for Capture mode to
recognize the trigger event on the CCPx
pin, Timer1 must be clocked from the
instruction clock (FOSC/4) or from an
external clock source.
21.3.4 CCP PRESCALER
There are four prescaler settings specified by the
MODE<3:0> bits of the CCPxCON register. Whenever
the CCP module is turned off, or the CCP module is not
in Capture mode, the prescaler counter is cleared. Any
Reset will clear the prescaler counter.
Switching from one capture prescaler to another does not
clear the prescaler and may generate a false interrupt. To
avoid this unexpected operation, turn the module off by
clearing the CCPxCON register before changing the
prescaler. Example 21-1 demonstrates the code to
perform this function.
EXAMPLE 21-1: CHANGING BETWEEN
CAPTURE PRESCALERS
BANKSEL CCPxCON ;Set Bank bits to point
;to CCPxCON
CLRF CCPxCON ;Turn CCP module off
MOVLW NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
MOVWF CCPxCON ;Load CCPxCON with this
;value
21.3.5 CAPTURE DURING SLEEP
Capture mode depends upon the Timer1 module for
proper operation. There are two options for driving the
Timer1 module in Capture mode. It can be driven by the
instruction clock (FOSC/4), or by an external clock source.
When Timer1 is clocked by FOSC/4, Timer1 will not
increment during Sleep. When the device wakes from
Sleep, Timer1 will continue from its previous state.
Capture mode will operate during Sleep when Timer1
is clocked by an external clock source.
21.4 Compare Mode
The Compare mode function described in this section
is available and identical for all CCP modules.
Compare mode makes use of the 16-bit Timer1
resource. The 16-bit value of the CCPRxH:CCPRxL
register pair is constantly compared against the 16-bit
value of the TMRxH:TMRxL register pair. When a
match occurs, one of the following events can occur:
• Toggle the CCPx output, clear TMRx
• Toggle the CCPx output
• Set the CCPx output
• Clear the CCPx output
• Pulse output
• Pulse output, clear TMRx
The action on the pin is based on the value of the
MODE<3:0> control bits of the CCPxCON register. At
the same time, the interrupt flag CCPxIF bit is set, and
an ADC conversion can be triggered, if selected.
All Compare modes can generate an interrupt and
trigger an ADC conversion. When MODE = 4'b0001
or 4'b1011, the CCP resets the TMR register pair.
Figure 21-2 shows a simplified diagram of the compare
operation.
FIGURE 21-2:
COMPARE MODE
OPERATION BLOCK
DIAGRAM
CCPxMODE<3:0>
Mode Select
Set CCPxIF Interrupt Flag
4 ^(PIR6)
CCPRxH CCPRxL
PPS
RxyPPS
Q S _Output
R ^Logic
TRIS
Output Enable
Match
Comparator
TMR1H TMR1L
Auto-conversion Trigger
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 270