PIC18LF24K Datasheet, PDF (344/594 Pages) –

PIC18(L)F26/45/46K40
26.6 I²C Mode Overview
The Inter-Integrated Circuit (I²C) bus is a multi-master
serial data communication bus. Devices communicate
in a master/slave environment where the master
devices initiate the communication. A slave device is
controlled through addressing. Figure 26-9 is a block
diagram of the I²C interface module in Master mode.
Figure 26-10 is a diagram of the I²C interface module
in Slave mode.
FIGURE 26-9:
MSSP BLOCK DIAGRAM (I²C MASTER MODE)
SDA
SSPxDATPPS⁽¹⁾
PPS
SDA in
RxyPPS⁽¹⁾
PPS
Read
Internal
data bus
Write
SSPxBUF
SSPSR
MSb
Shift
Clock
LSb
[SSPM<3:0>]
Baud Rate
Generator
(SSPxADD)
SSPxCLKPPS⁽²⁾
SCL
PPS
Start bit, Stop bit,
Acknowledge
Generate (SSPxCON2)
PPS
RxyPPS⁽²⁾
SCL in
Bus Collision
Start bit detect,
Stop bit detect
Write collision detect
Clock arbitration
State counter for
end of XMIT/RCV
Address Match detect
Set/Reset: S, P, SSPxSTAT, WCOL, SSPOV
Reset SEN, PEN (SSPxCON2)
Set SSP1IF, BCL1IF
Note 1: SDA pin selections must be the same for input and output
2: SCL pin selections must be the same for input and output
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 344