PIC18LF24K Datasheet, PDF (537/594 Pages) –

PIC18(L)F26/45/46K40
37.3 DC Characteristics
TABLE 37-1: SUPPLY VOLTAGE
PIC18LF26/45/46K40
Standard Operating Conditions (unless otherwise stated)
PIC18F26/45/46K40
Param.
No.
Sym.
Characteristic
Min. Typ.† Max. Units
Conditions
Supply Voltage
D002 VDD
1.8 —
3.6
V FOSC  16 MHz
2.5 —
3.6
V FOSC  16 MHz
3.0 —
3.6
V FOSC  32 MHz
D002 VDD
RAM Data Retention⁽¹⁾
2.3 —
5.5
V FOSC  16 MHz
2.5 —
5.5
V FOSC 16 MHz
3.0 —
5.5
V FOSC  32 MHz
D003 VDR
1.5 —
—
V Device in Sleep mode
D003 VDR
Power-on Reset Release Voltage⁽²⁾
1.7 —
—
V Device in Sleep mode
D004 VPOR
— 1.6
—
V BOR or LPBOR disabled⁽³⁾
D004 VPOR
— 1.6
—
V BOR or LPBOR disabled⁽³⁾
Power-on Reset Rearm Voltage⁽²⁾
D005 VPORR
— 0.8
D005 VPORR
— 1.5
VDD Rise Rate to ensure internal Power-on Reset signal⁽²⁾
D006 SVDD
0.05 —
D006 SVDD
0.05 —
—
V BOR or LPBOR disabled⁽³⁾
—
V BOR or LPBOR disabled⁽³⁾
— V/ms BOR or LPBOR disabled⁽³⁾
— V/ms BOR or LPBOR disabled⁽³⁾
† Data in “Typ.” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: This is the limit to which VDD can be lowered in Sleep mode without losing RAM data.
2: See Figure 37-3, POR and POR REARM with Slow Rising VDD.
3: Please see Table 37-11 for BOR and LPBOR trip point information.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 537