PIC18LF24K Datasheet, PDF (338/594 Pages) –

PIC18(L)F26/45/46K40
26.5.1 SPI MASTER MODE
The master can initiate the data transfer at any time
because it controls the SCK line. The master
determines when the slave (Processor 2, Figure 26-3)
is to broadcast data by the software protocol.
In Master mode, the data is transmitted/received as
soon as the SSPxBUF register is written to. If the SPI
is only going to receive, the SDO output could be
disabled (programmed as an input). The SSPSR
register will continue to shift in the signal present on the
SDI pin at the programmed clock rate. As each byte is
received, it will be loaded into the SSPxBUF register as
if a normal received byte (interrupts and Status bits
appropriately set).
The clock polarity is selected by appropriately
programming the CKP bit of the SSPxCON1 register
and the CKE bit of the SSPxSTAT register. This then,
would give waveforms for SPI communication as
shown in Figure 26-4, Figure 26-6, Figure 26-7 and
Figure 26-8, where the MSB is transmitted first. In
Master mode, the SPI clock rate (bit rate) is user
programmable to be one of the following:
• FOSC/4 (or TCY)
• FOSC/16 (or 4 * TCY)
• FOSC/64 (or 16 * TCY)
• Timer2 output/2
• FOSC/(4 * (SSPxADD + 1))
Figure 26-4 shows the waveforms for Master mode.
When the CKE bit is set, the SDO data is valid before
there is a clock edge on SCK. The change of the input
sample is shown based on the state of the SMP bit. The
time when the SSPxBUF is loaded with the received
data is shown.
Note:
In Master mode the clock signal output to
the SCK pin is also the clock signal input
to the peripheral. The pin selected for out-
put with the RxyPPS register must also be
selected as the peripheral input with the
SSPxCLKPPS register.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 338