PIC18LF24K Datasheet, PDF (300/594 Pages) –

PIC18(L)F26/45/46K40
24.2.4.2 Asynchronous Steering Mode
In Asynchronous mode (MODE<2:0> bits = 000,
Register 24-1), steering takes effect at the end of the
instruction cycle that writes to STR. In Asynchronous
Steering mode, the output signal may be an incomplete
waveform (Figure 24-10). This operation may be useful
when the user firmware needs to immediately remove
a signal from the output pin.
FIGURE 24-10: EXAMPLE OF ASYNCHRONOUS STEERING (MODE<2:0>= 000)
CWG1
INPUT
End of Instruction Cycle
STRA
End of Instruction Cycle
CWG1A
CWG1A Follows CWG1 data input
24.2.4.3 Start-up Considerations
The application hardware must use the proper external
pull-up and/or pull-down resistors on the CWG output
pins. This is required because all I/O pins are forced to
high-impedance at Reset.
The POLy bits (Register 24-2) allow the user to choose
whether the output signals are active-high or active-
low.
 2016 Microchip Technology Inc.
Preliminary
DS40001816C-page 300