SH7047 Datasheet, PDF (97/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 5 Exception Processing
5.1 Overview
5.1.1 Types of Exception Processing and Priority
Exception processing is started by four sources: resets, address errors, interrupts and instructions
and have the priority, as shown in table 5.1. When several exception processing sources occur at
once, they are processed according to the priority.
Table 5.1 Types of Exception Processing and Priority
Exception Source
Priority
Reset
Power-on reset
High
Address
error
Manual reset
CPU address error and AUD address error*¹
DTC address error
Interrupt NMI
User break
H-UDI*¹
IRQ
On-chip peripheral • Multifunction timer unit (MTU)
modules:
• A/D converter 0 and 1 (A/D0, A/D1)
• Data transfer controller (DTC)
• Compare match timer 0 and 1 (CMT0, CMT1)
• Watchdog timer (WDT)
• Input/output port (I/O) (MTU)
• Serial communication interface 2, 3, and 4 (SCI2,
SCI3, and SCI4)
• Motor management timer (MMT)
• Input/output port (I/O) (MMT)
• Controller area network 2 (HCAN 2)
Instructions Trap instruction (TRAPA instruction)
General illegal instructions (undefined code)
Illegal slot instructions (undefined code placed directly after a delay
Low
branch instruction*² or instructions that rewrite the PC*³)
Notes: 1. For flash version only
2. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF, and
BRAF.
3. Instructions that rewrite the PC: JMP, JSR, BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, and BRAF.
Rev. 2.00, 09/04, page 57 of 720