SH7047 Datasheet, PDF (149/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 8 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 8.1 shows a block diagram of the DTC.
The DTC’s register information is stored in the on-chip RAM. When the DTC is used, the RAME
bit in SYSCR must be set to 1.
8.1 Features
• Transfer possible over any number of channels
• Three transfer modes
Normal, repeat, and block transfer modes available
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 32-bit address space possible
• Activation by software is possible
• Transfer can be set in byte, word, or longword units
• The interrupt that activated the DTC can be requested to the CPU
• Module standby mode can be set
Rev. 2.00, 09/04, page 109 of 720