SH7047 Datasheet, PDF (375/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value
1
CKS1
0
0
CKS0
0
R/W Description
R/W Clock Select 1 and 0
R/W These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10:Pφ/32 clock (n = 2)
11:Pφ/128 clock (n = 3)
For the relation between the bit rate register setting
and the baud rate, see section 12.3.9, Bit Rate
Register (BRR). n is the decimal display of the value
of n in BRR (see section 12.3.9, Bit Rate Register
(BRR)).
12.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 12.7, SCI Interrupts.
Initial
Bit Bit Name Value
7
TIE
0
6
RIE
0
5
TE
0
4
RE
0
R/W Description
R/W Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
R/W Transmit Enable
When this bit is set to 1, transmission is enabled.
R/W Receive Enable
When this bit is set to 1, reception is enabled.
Rev. 2.00, 09/04, page 335 of 720