SH7047 Datasheet, PDF (60/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

2.4 Instruction Features
2.4.1 RISC-Type Instruction Set
All instructions are RISC type. This section details their functions.
16-Bit Fixed Length: All instructions are 16 bits long, increasing program code efficiency.
One Instruction per State: The microprocessor can execute basic instructions in one state using
the pipeline system. One state is 25 ns at 40 MHz.
Data Length: Longword is the standard data length for all operations. Memory can be accessed in
bytes, words, or longwords. Byte or word data accessed from memory is sign-extended and
handled as longword data. Immediate data is sign-extended for arithmetic operations or zero-
extended for logic operations. It also is handled as longword data.
Table 2.2 Sign Extension of Word Data
CPU of This LSI
Description
MOV.W
ADD
.DATA.W
@(disp,PC),R1 Data is sign-extended to 32
R1,R0
bits, and R1 becomes
H'00001234. It is next
.........
operated upon by an ADD
H'1234
instruction.
Note: @(disp, PC) accesses the immediate data.
Example of Conventional CPU
ADD.W #H'1234,R0
Load-Store Architecture: Basic operations are executed between registers. For operations that
involve memory access, data is loaded to the registers and executed (load-store architecture).
Instructions such as AND that manipulate bits, however, are executed directly in memory.
Delayed Branch Instructions: Unconditional branch instructions are delayed branch instructions.
With a delayed branch instruction, the branch is taken after execution of the instruction following
the delayed branch instruction. This reduces the disturbance of the pipeline control in case of
branch instructions. There are two types of conditional branch instructions: delayed branch
instructions and ordinary branch instructions.
Table 2.3 Delayed Branch Instructions
CPU of This LSI
BRA
TRGET
ADD
R1,R0
Description
Executes the ADD before
branching to TRGET.
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Rev. 2.00, 09/04, page 20 of 720