SH7047 Datasheet, PDF (165/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Block Transfer Mode: Performs the transfer of one block for each one activation. Either the
transfer source or transfer destination is designated as the block area.
The block length is specified between 1 and 65536. When the transfer of one block ends, the
initial state of the block size counter and the address register specified as the block area is restored.
The other address register is then incremented, decremented, or left fixed.
From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a
CPU interrupt is requested.
Table 8.4 Block Transfer Mode Register Functions
Register
DTMR
DTCRA
DTCRB
DTSAR
DTDAR
Function
Operation mode
control
Transfer count
Block length
Transfer source
address
Transfer destination
address
Values Written Back upon a Transfer Information Write
DTMR
DTCRA – 1
(Not written back)
(DTS = 0) Increment/ decrement/ fixed
(DTS = 1) DTSAR initial value
(DTS = 0) DTDAR initial value
(DTS = 1) Increment/ decrement/ fixed
DTSAR
or
DTDAR
First block
•
•
Block area
•
Transfer
Nth block
DTDAR
or
DTSAR
Figure 8.8 Memory Mapping in Block Transfer Mode
Rev. 2.00, 09/04, page 125 of 720