SH7047 Datasheet, PDF (10/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator....................................................................... 51
4.1 Oscillator........................................................................................................................... 52
4.1.1 Connecting a Crystal Resonator........................................................................... 52
4.1.2 External Clock Input Method .............................................................................. 53
4.2 Function for Detecting the Oscillator Halt........................................................................ 54
4.3 Usage Notes ...................................................................................................................... 55
4.3.1 Note on Crystal Resonator................................................................................... 55
4.3.2 Notes on Board Design ........................................................................................ 55
Section 5 Exception Processing......................................................................... 57
5.1 Overview........................................................................................................................... 57
5.1.1 Types of Exception Processing and Priority ........................................................ 57
5.1.2 Exception Processing Operations ........................................................................ 58
5.1.3 Exception Processing Vector Table ..................................................................... 59
5.2 Resets................................................................................................................................ 61
5.2.1 Types of Reset ..................................................................................................... 61
5.2.2 Power-On Reset ................................................................................................... 61
5.2.3 Manual Reset ....................................................................................................... 62
5.3 Address Errors .................................................................................................................. 63
5.3.1 The Cause of Address Error Exception................................................................ 63
5.3.2 Address Error Exception Processing ................................................................... 64
5.4 Interrupts........................................................................................................................... 65
5.4.1 Interrupt Sources.................................................................................................. 65
5.4.2 Interrupt Priority Level ........................................................................................ 66
5.4.3 Interrupt Exception Processing ............................................................................ 66
5.5 Exceptions Triggered by Instructions ............................................................................... 67
5.5.1 Types of Exceptions Triggered by Instructions ................................................... 67
5.5.2 Trap Instructions.................................................................................................. 67
5.5.3 Illegal Slot Instructions........................................................................................ 68
5.5.4 General Illegal Instructions.................................................................................. 68
5.6 Cases when Exception Sources Are Not Accepted........................................................... 69
5.6.1 Immediately after a Delayed Branch Instruction ................................................. 69
5.6.2 Immediately after an Interrupt-Disabled Instruction............................................ 69
5.7 Stack Status after Exception Processing Ends .................................................................. 70
5.8 Usage Notes ...................................................................................................................... 71
5.8.1 Value of Stack Pointer (SP) ................................................................................. 71
5.8.2 Value of Vector Base Register (VBR)................................................................. 71
5.8.3 Address Errors Caused by Stacking of Address Error Exception Processing...... 71
Section 6 Interrupt Controller (INTC)............................................................... 73
6.1 Features............................................................................................................................. 73
6.2 Input/Output Pins.............................................................................................................. 75
6.3 Register Descriptions........................................................................................................ 75
Rev. 2.00, 09/04, page x of xl