SH7047 Datasheet, PDF (275/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Timer output control register settings
OLSN bit: 0 (initial output: high; active level: low)
OLSP bit: 0 (initial output: high; active level: low)
TCNT_3, 4 value
TCNT_3
TCNT_4
Positive phase
output
Negative phase
output
TDDR
TGR_4
Initial output
Active level
Time
Complementary
PWM mode
(TMDR setting)
TCNT_3, 4 count start
(TSTR setting)
Figure 10.39 Example of Initial Output in Complementary PWM Mode (2)
Rev. 2.00, 09/04, page 235 of 720