SH7047 Datasheet, PDF (664/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

25.3.2 Clock Timing
Table 25.4 shows the clock timing.
Table 25.4 Clock Timing
Conditions: V_CC = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to
+75°C (Standard product)*, T_a = –40°C to +85°C (Wide temperature-range
product)*.
Item
Symbol Min
Operating frequency 50MHz operation* f_op
4
40MHz operation*
4
Clock cycle time
50MHz operation*
t
cyc
20
40MHz operation*
25
Clock low-level pulse width
t_CL
4
Clock high-level pulse width
t_CH
4
Clock rise time
t_CR
—
Clock fall time
t_CF
—
EXTAL clock input 50MHz operation* f_EX
4
frequency
40MHz operation*
4
EXTAL clock input
50MHz operation*
t
EXcyc
80
cycle time
40MHz operation*
100
EXTAL clock input
50MHz operation*
t
EXL
35
low-level pulse width 40MHz operation*
45
EXTAL clock input 50MHz operation* t_EXH
35
high-level pulse width 40MHz operation*
45
EXTAL clock input rise time
t_EXR
—
EXTAL clock input fall time
t_EXF
—
Reset oscillation settling time
t
10
OSC1
Standby return oscillation settling time
t
10
OSC2
Clock cycle time for
peripheral modules
t
25
pcyc
Max Unit Figures
50
MHz Figure 25.2
40
250
ns
250
—
ns
—
ns
5
ns
5
ns
12.5 MHz Figure 25.3
10.0
250
ns
250
—
ns
—
—
ns
—
5
ns
5
ns
—
ms Figure 25.4
—
ms
500
ns
Note: * See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
Rev. 2.00, 09/04, page 624 of 720