SH7047 Datasheet, PDF (450/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.2 Input/Output Pins
Table 15.1 shows the HCAN2's pins. When using the functions of these external pins, the pin
function controller (PFC) must also be set in line with the HCAN2 settings.
When using HCAN2 pins, settings must be made in HCAN2 configuration mode.
Table 15.1 HCAN2 Pins
Name
HCAN2 transmit data pin
HCAN2 receive data pin
Abbreviation
HTxD1
HRxD1
Input/Output
Output
Input
Function
CAN bus transmission pin
CAN bus reception pin
A bus driver is necessary for the interface between the pins and the CAN bus. A Renesas
HA13721 compatible model is recommended.
15.3 Register Descriptions
The HCAN2 has the following registers. For details on register addresses and register states during
each process, refer to appendix A, Internal I/O Register.
• Master control register (MCR)
• General status register (GSR)
• Bit timing configuration register 1 (HCAN2_BCR1*)
• Bit timing configuration register 0 (HCAN2_BCR0*)
• Interrupt request register (IRR)
• Interrupt mask register (IMR)
• Error counter register (TEC/REC)
• Transmit wait registers (TXPR1, TXPR0)
• Transmit wait cancel registers (TXCR1, TXCR0)
• Transmit acknowledge registers (TXACK1, TXACK0)
• Abort acknowledge registers (ABACK1, ABACK0)
• Receive complete registers (RXPR1, RXPR0)
• Remote request registers (RFPR1, RFPR0)
• Mailbox interrupt mask registers (MBIMR1, MBIMR0)
• Unread message status registers (UMSR1, UMSR0)
• Mailboxes (16-bit × 10 registers × 32 sets) (MB0 to MB31)
• Timer counter register (TCNTR)
• Timer control register (TCR)
• Timer status register (TSR)
Rev. 2.00, 09/04, page 410 of 720