SH7047 Datasheet, PDF (472/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.9 Transmit Wait Cancel Registers (TXCR1, TXCR0)
TXCR1 and TXCR0 are 16-bit registers that control cancellation of transmit wait messages in
mailboxes.
• TXCR1
Bit Bit Name
15 TXCR31
14 TXCR30
13 TXCR29
12 TXCR28
11 TXCR27
10 TXCR26
9
TXCR25
8
TXCR24
7
TXCR23
6
TXCR22
5
TXCR21
4
TXCR20
3
TXCR19
2
TXCR18
1
TXCR17
0
TXCR16
Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Cancel the transmit wait message in the
corresponding mailboxes from 16 to 31. When
TXCRn (n = 16 to 31) is set to 1, the transmit wait
message in mailbox n is canceled.
[Clearing condition]
• Completion of TXPR clearing (when transmit
message is canceled normally), or normal end
process is carried out (when transmit message is
being transmitted, thereby unable to be canceled)
To clear the corresponding bit in TXPR, 1 must be
written to the corresponding bit TXCR. When
cancellation has succeeded, the HCAN2 clears the
corresponding TXPR/TXCR bits, and sets the
corresponding ABACK bit. However, once a mailbox
has started transmission, it cannot be canceled by
this bit.
Notes: 1. 1 can be written only when the mailbox is
configured as a transmit mailbox.
2. Restrictions apply to the use of the
mailbox 31 for transmission. Carefully
read section 15.8, Usage Notes.
Rev. 2.00, 09/04, page 432 of 720