SH7047 Datasheet, PDF (496/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W
12
TCR12
0
R/W
11
TCR11
0
R/W
10
TCR10
0
R/W
9
TCR9
0
R/W
8 to 6 —
All 0 R
Description
Timestamp Control for Transmission
Specifies if the timestamp operates in corresponding
TXPR bit or TXACK bit. Use ICR1 for timestamp in
transmission.
0: Timestamp in TXPR bit
1: Timestamp in TXACK bit
Timer Clear/Set Control by TCMR0
Specifies if the timer is to be cleared and set to LOSR
when TCMR0 matches TCNTR.
Note: TCMR0 is capable of generating an interrupt
signal to the host processor via IRR14.
0: Timer is not cleared by TCMR0
1: Timer is cleared and set to LOSR by TCMR0
Timer Clear/Set Control by CCM
Specifies if the timer is to be cleared and set to LOSR by
CAN-ID compare match (CCM) when a mailbox receives
a message, only when the CCM bit of the corresponding
mailbox and this bit are both set.
Note: CCM cannot generate an interrupt signal. This
can be performed by IRR1 or IRR2.
0: Timer cannot be cleared by CCM
1: Timer is cleared by CCM and set to LOSR
ICR0 Automatic Disable by CCM
Specifies if ICR0 is to be disabled by CAN-ID compare
match (CCM) when a mailbox stores a receive message.
When a mailbox stores a receive message, TCR14 (bit
14) of this register is automatically cleared and the ICR0
value is retained, only if the CCM bit of the
corresponding mailbox and this bit are both set.
0: TCR14 is not cleared
1: TCR14 is automatically cleared
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/04, page 456 of 720