SH7047 Datasheet, PDF (55/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

General registers (Rn)
31
0
R0^*1
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15, SP (hardware stack pointer)^*2
Status register (SR)
31
9 87 6 5 4 3 210
M Q I3 I2 I1 I0
ST
Global base register (GBR)
31
0
GBR
Vector base register (VBR)
31
0
VBR
Multiply-accumulate register (MAC)
31
0
MACH
MACL
Procedure register (PR)
31
0
PR
Program counter (PC)
31
0
PC
Notes: *1 R0 functions as an index register in the indirect indexed register addressing mode and indirect indexed GBR
addressing mode. In some instructions, R0 functions as a fixed source register or destination register.
*2 R15 functions as a hardware stack pointer (SP) during exception processing.
Figure 2.1 CPU Internal Registers
Rev. 2.00, 09/04, page 15 of 720