SH7047 Datasheet, PDF (291/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Pφ
External
clock
TCNT input
clock
Falling edge
Rising edge
Falling edge
TCNT
N-1
N
N+1
Figure 10.56 Count Timing in External Clock Operation (Phase Counting Mode)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match
signal is not generated until the TCNT input clock is generated.
Figure 10.57 shows output compare output timing (normal mode and PWM mode) and Figure
10.58 shows output compare output timing (complementary PWM mode and reset synchronous
PWM mode).
Pφ
TCNT input
clock
TCNT
N
N+1
TGR
N
Compare
match signal
TIOC pin
Figure 10.57 Output Compare Output Timing (Normal Mode/PWM Mode)
Rev. 2.00, 09/04, page 251 of 720