SH7047 Datasheet, PDF (234/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.4 Operation
10.4.1 Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, synchronous counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Always set the MTU external pins function using the pin function controller (PFC).
Counter Operation: When one of bits CST0 to CST4 is set to 1 in TSTR, the TCNT counter for
the corresponding channel begins counting. TCNT can operate as a free-running counter, periodic
counter, for example.
1. Example of Count Operation Setting Procedure
Figure 10.3 shows an example of the count operation setting procedure.
Operation selection
Select counter clock [1]
Periodic counter
Select counter clearing
source
[2]
Select output compare _[3]
register
Set period
[4]
Start count operation ^[5]
<Periodic counter>
Free-running counter
Start count operation [5]
<Free-running counter>
[1] Select the counter clock
with bits TPSC2 to TPSC0
in TCR. At the same time,
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
[2] For periodic counter
operation, select the TGR
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
[3] Designate the TGR
selected in [2] as an output
compare register by means
of TIOR.
[4] Set the periodic counter
cycle in the TGR selected
in [2].
[5] Set the CST bit in TSTR to
1 to start the counter
operation.
Figure 10.3 Example of Counter Operation Setting Procedure
Rev. 2.00, 09/04, page 194 of 720