SH7047 Datasheet, PDF (18/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.17 Timer Counter Register (TCNTR)....................................................................... 454
15.3.18 Timer Control Register (TCR)............................................................................. 455
15.3.19 Timer Status Register (TSR)................................................................................ 457
15.3.20 Local Offset Register (LOSR) ............................................................................. 458
15.3.21 Input Capture Registers 0 and 1 (ICR0, ICR1).................................................... 459
15.3.22 Timer Compare Match Registers 0 and 1 (TCMR0 and TCMR1) ...................... 459
15.4 Operation .......................................................................................................................... 460
15.4.1 Hardware and Software Resets ............................................................................ 460
15.4.2 Initialization after Hardware Reset ...................................................................... 460
15.4.3 Message Transmission by Event Trigger............................................................. 466
15.4.4 Message Reception .............................................................................................. 469
15.4.5 Mailbox Reconfiguration..................................................................................... 472
15.4.6 HCAN2 Sleep Mode............................................................................................ 473
15.4.7 HCAN2 Halt Mode.............................................................................................. 476
15.5 Interrupt Sources............................................................................................................... 477
15.6 DTC Interface ................................................................................................................... 478
15.7 CAN Bus Interface............................................................................................................ 479
15.8 Usage Notes ...................................................................................................................... 479
15.8.1 Time Trigger Transmit Setting/Timer Operation Disabled.................................. 479
15.8.2 Reset .................................................................................................................... 479
15.8.3 HCAN2 Sleep Mode............................................................................................ 480
15.8.4 Interrupts.............................................................................................................. 480
15.8.5 Error Counters ..................................................................................................... 480
15.8.6 Register Access.................................................................................................... 480
15.8.7 Register in Standby Modes .................................................................................. 480
15.8.8 Transmission Cancellation during SOF or Intermission...................................... 480
15.8.9 Cases when the Transmit Wait Register
(TXPR) is Set during Transfer of EOF ................................................................ 481
15.8.10 Limitation on Access to the Local Acceptance Filter Mask (LAFM).................. 481
15.8.11 Notes on Using Auto Acknowledge Mode .......................................................... 481
15.8.12 Notes on Usage of the Transmit Wait Cancel Register (TXCR) ......................... 481
15.8.13 Setting and Cancellation of Transmission during Bus-Idle State ........................ 482
15.8.14 Releasing HCAN2 Reset ..................................................................................... 482
15.8.15 Accessing Mailboxes When HCAN2 Is in Sleep Mode ...................................... 482
15.8.16 Module Standby Mode Setting ............................................................................ 482
Section 16 Motor Management Timer (MMT) ................................................. 483
16.1 Features............................................................................................................................. 483
16.2 Input/Output Pins.............................................................................................................. 485
16.3 Register Descriptions........................................................................................................ 486
16.3.1 Timer Mode Register (MMT_TMDR) ................................................................ 487
16.3.2 Timer Control Register (TCNR).......................................................................... 488
16.3.3 Timer Status Register (MMT_TSR) .................................................................... 489
Rev. 2.00, 09/04, page xviii of xl