SH7047 Datasheet, PDF (136/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Figure 7.1 shows a block diagram of the UBC.
Module bus
Bus
interface
UBCR
UBBR ^{UBAMRH UBARH}
UBAMRL UBARL
Break condition
comparator
User break
interrupt
generating
circuit
Interrupt request
Trigger output
generating
circuit
Interrupt controller
UBCTRG pin output
UBC
UBARH, UBARL: User break address registers H, L
UBAMRH, UBAMRL: User break address mask registers H, L
UBBR:
User break bus cycle register
UBCR:
User break control register
Figure 7.1 User Break Controller Block Diagram
Rev. 2.00, 09/04, page 96 of 720