SH7047 Datasheet, PDF (353/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.9.4 Operation
Input Level Detection Operation: If the input conditions set by the ICSR1 occur on any of the
POE pins, all high-current pins become high-impedance state. However, only when the general
input/output function or MTU function is selected, the large-current pin is in the high-impedance
state.
1. Falling Edge Detection
When a change from high to low level is input to the POE pins.
2. Low-Level Detection
Figure 10.115 shows the low-level detection operation. Sixteen continuous low levels are
sampled with the sampling clock established by the ICSR1. If even one high level is detected
during this interval, the low level is not accepted.
Furthermore, the timing when the large-current pins enter the high-impedance state from the
sampling clock is the same in both falling-edge detection and in low-level detection.
8/16/128 clock
cycles
Pφ
Sampling
clock
POE input
PE9/
TIOC3B
High-impedance
state*
When low level is
Flag set
sampled at all points ¹
2
3
16 _{(POE received)}
When high level is
sampled at least once
1
2
13 Flag not set
Note: * Other large-current pins (PE11/TIOC3D, PE12/TIOC4A, PE13/TIOC4B/MRES, PE14/TIOC4C,
PE15/TIOC4D/IRQOUT) also go to the high-impedance state at the same timing.
Figure 10.115 Low-Level Detection Operation
Rev. 2.00, 09/04, page 313 of 720