SH7047 Datasheet, PDF (82/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

2.6 Processing States
2.6.1 State Transitions
The CPU has five processing states: reset, exception processing, bus release, program execution
and power-down. Figure 2.4 shows the transitions between the states.
From any state
when RES = 0
and HSTBY = 1
From any state when
RES = 1, MRES = 0,
and HSTBY = 1
RES = 0
HSTBY = 1
Power-on reset state
RES = 0
Manual reset state
When an internal power-on
reset by WDT or internal
manual reset by
WDT occurs
RES = 1
Exception
processing state
RES = 1,
MRES = 1
Bus request
cleared
Bus request
generated
Exception
processing
source
occurs
Exception
processing
ends
Bus release state
Bus request
cleared
Bus request
generated
Program execution state
Reset state
NMI interrupt or IRQ
interrupt occurs
Bus request Bus request
generated
cleared
SSBY bit cleared
for SLEEP
instruction
SSBY bit set
for SLEEP
instruction
Sleep mode
Software standby mode
Hardware standby mode
From any state when
RES = 0 and HSTBY = 0
Figure 2.4 Transitions between Processing States
Power-down mode
Rev. 2.00, 09/04, page 42 of 720