SH7047 Datasheet, PDF (494/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Table 15.3 Message Data Area Configuration in TCT Bit Setting
Data Bus
Access Field
Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size Name
H'108 + Cycle_Counter (first Rx/Tx Byte) MSG_DATA_1
N*32
Byte or Data
word
H'10A + TCNTR[7:0]
N*32
TCNTR[15:8]
H'10C + MSG_DATA_4
N*32
MSG_DATA_5
H'10E + MSG_DATA_6
N*32
MSG_DATA_7
15.3.17 Timer Counter Register (TCNTR)
TCNTR is a 16-bit readable/writable register. This allows the CPU to monitor the timer counter
value and set the free-running timer counter value. Setting the TCR11 bit to 1 allows TCMR0 to
clear the timer when a timer value and TCMR0 (timer compare match 0) matched and the value is
set to LOSR (local offset register). Then counting starts.
Initial
Bit Bit Name Value R/W
15 to 0 TCNTR15 to All 0 R/W
TCNTR0
Description
Timer Count Register
Setting bit 15 (TCR15) in the timer control register (TCR)
to 1 enables these bits to be used as a free-running
counter. The counter value can be cleared depending on
the compare match condition.
Rev. 2.00, 09/04, page 454 of 720