SH7047 Datasheet, PDF (541/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

The on-chip A/D converter can be activated when TCNT matches TPDR or 2Td. When the TGF
flag in the timer status register (TSR) is set to 1 as a result of either match corresponding, a request
to start A/D conversion is sent to the A/D converter. If the start-conversion trigger of the MMT is
selected in the A/D converter at that time, A/D conversion starts up.
16.6 Operation Timing
16.6.1 Input/Output Timing
TCNT and TDCNT Count Timing: Figure 16.8 shows the TCNT and TDCNT count timing.
Pφ
TCNT,
TDCNT
N–3 N–2 N–1 N N+1 N+2 N+3 N+4
Figure 16.8 Count Timing
TCNT Counter Clearing Timing: Figure 16.9 shows the timing of TCNT counter clearing by an
external signal.
Pφ
Counter clear
signal
TCNT
N – 3 N – 2 N – 1 N N + 1 2Td 2Td + 1 2Td + 2
TDDR
Td
Figure 16.9 TCNT Counter Clearing Timing
Rev. 2.00, 09/04, page 501 of 720