SH7047 Datasheet, PDF (604/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Figure 19.8 shows a sample procedure for flash memory block area overlapping.
1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range H'FFFFD000 to
H'FFFFDFFF.
2. The flash memory area to be overlapped is selected by RAMER from a 4-kbyte area of the
EB0 to EB7 blocks.
3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM
addresses.
4. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all flash
memory blocks (emulation protection). In this state, setting the P or E bit in FLMCR1 to 1
does not cause a transition to program mode or erase mode.
5. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm.
6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
is needed in the overlapped RAM.
H'00000
EB0
H'01000
EB1
H'02000
EB2
H'03000
EB3
H'04000
EB4
H'05000
EB5
H'06000
EB6
H'07000
EB7
H'08000
This area can be accessed from
both the flash memory addresses
and RAM addresses.
Flash Memory
EB8 to EB11
On-chip RAM
H'FFFFD000
H'FFFFDFFF
H'3FFFF
H'FFFFFFFF
Figure 19.8 Example of RAM Overlap Operation (RAM[2:0] = b'000)
Rev. 2.00, 09/04, page 564 of 720